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80504 jo im no.7941-1/19 ver.1.00 00000 LC87F5564A overview the LC87F5564A is 8-bit single chip microcontroller with the following one-chip features : ? cpu : operable at a minimum bus cycle time of 100ns ? on-chip flash rom capacity : 64k-bytes (on-board rewritable) ? on-chip ram capacity : 1k-bytes ? two high performance 16-bit timer/counters (can be divided into 8-bit timers) ? four 8-bit timers with prescalers ? timer for use as date/time clock ? one synchronous serial i/o port (with automatic block transmit/receive function) ? one asynchronous/synchronous serial i/o port ? 12-bit pwm 2 ? 12-channel 8-bit ad converter ? high speed clock counter ? system clock divider ? 20-source 10-vectored interrupt system features read only memory (flash rom) ? single 5v power supply, on-board writeable ? block erase in 128-byte units ? 65536 8-bits (LC87F5564A) minimum bus cycle time ? 100ns (10mhz) note : bus cycle time indicates the speed to read rom. minimum instruction cycle time ? 300ns (10mhz) ordering number : enn7941 cmos ic from 64k-byte, ram 1k-byte on chip 8-bit 1-chip microcontroller
LC87F5564A no.7941-2/19 ports ? input/output ports input/output programmable for each bit individually 27 (p1n, p2n, p3n, p70 to p73) data direction programmable in nibble units 8 (p0n) ? input ports 2 (xt1, xt2) ? pwm output ports 2 (pwm0, pwm1) ? oscillator pins 2 (cf1, cf2) ? reset pin 1 (res ) ? power supply 6 (v ss 1 to 3, v dd 1 to 3) timer ? timer 0 : 16-bit timer/counter with capture register mode 0 : two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register mode 1 : 8-bit timer with 8-bit programmable prescale r and 8-bit capture register + 8-bit counter with 8-bit capture register mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register mode 3 : 16-bit counter with 16-bit capture register ? timer 1 : pwm/16-bit timer/counter with toggle output mode 0 : 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output) mode 1 : two 8-bit pwm mode 2 : 16-bit timer/counter (with toggle output) toggle output is also possible by using the lower order 8-bits. mode 3 : 16-bit timer (with toggle output) the lower order 8-bits can be used as pwm output. ? timer 4 : 8-bit timer with 6-bit prescaler ? timer 5 : 8-bit timer with 6-bit prescaler ? timer 6 : 8-bit timer with 6-bit prescaler ? timer 7 : 8-bit timer with 6-bit prescaler ? base timer 1. clock for the base timer is selectable from sub- clock (32.768khz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. there can be five separate interrupt sources. high speed clock counter 1. maximum of 20mhz possible (when using a 10mhz main clock) 2. real-time output serial interface ? sio0 : 8-bit synchronous serial interface 1. lsb first/msb first-function available 2. an internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 256-bits) ? sio1 : 8-bit asynchronous/synchronous serial interface mode 0 : synchronous 8-bit serial i o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1 : asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tcyc) mode 2 : bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3 : bus mode 2 (start detection, 8 data bits, stop detection) ad converter ? 12-channel 8-bit ad converter pwm ? 2-channel synchronous variable 12-bit pwm remote receiver circuit (share with p73/int3/t0in terminal) ? noise rejection function (the filtering time of the noise rejection filter (1 tcyc/32 tcyc /128 tcyc) can be switched by program.)
LC87F5564A no.7941-3/19 watchdog timer ? external rc circuit is required. ? interrupt or system reset is activated when the timer overflows. interrupts ? 20-source and 10-vectored interrupt function : 1. three interrupt priorities, low (l), high (h) and highe st (x) are supported with multi-level nesting possible. during interrupt handling, an equal or lower level interrupt request is refused. 2. if interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority level : x > h > l ? for equal priority levels, vector w ith lowest address takes precedence. subroutine stack levels ? a maximum of 512 levels (set stack inside ram) multiplication and division ? 16-bits 8-bits (5 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) ? 16-bits 8-bits (8 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) oscillation circuits ? built-in rc oscillation circuit used for the system clock ? cf oscillation circuit used for the system clock ? crystal oscillation circuit used for the system clock ? built-in frequency variable rc oscillation circuit used for the system clock system clock divider ? operable on the lowest power consumption ? minimum instruction cycle time 300ns, 600ns, 1.2 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10mhz main clock) standby function ? halt mode the halt mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. this operation mode can be released by a system reset or an interrupt request. ? hold mode the hold mode stops program execution and all oscill ation circuits : cf, rc and crystal oscillations. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal (res ) 2. supply the selected level to at lease one of int0, int1, int2, int4 int5. 3. supply an interrupt condition to port 0. continued on next page.
LC87F5564A no.7941-4/19 continued from preceding page. ? x?tal hold mode the x?tal hold mode stops program execution and all peripheral circuits except for the base timer. the crystal oscillator maintains its state at hold mode inception. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal ( res ). 2. supply the selected level to at leas t one of int0, int1, int2, int4, int5 3. supply an interrupt condition to port 0. 4. supply an interrupt condition to the base timer circuit. shipping form ? qip48e ? sqfp48 development tools ? evaluation (eva) chip : lc876093 ? emulator : eva62s + ecb876600a + sub875500 + pod48qfp ? flash rom writer adapter : w87f5564q (qip48e), w87f5564sq (sqfp48) package dimensions package dimensions unit : mm unit : mm 3163b 3156
LC87F5564A no.7941-5/19 pin assignment pad coordinate values sqfp/qip name sqfp/qip name 1 p73/int3/t0in 25 p04/an4 2 res 26 p05/an5 3 xt1/an10 27 p06/an6 4 xt2/an11 28 p07/an7 5 v ss 1 29 p20/int4 6 cf1 30 p21/int4 7 cf2 31 p22/int4 8 v dd 1 32 p23/int4 9 p10/so0 33 p24/int5 10 p11/si0/sb0 34 p25/int5 11 p12/sck0 35 p26/int5 12 p13/so1 36 p27/int5 13 p14/si1/sb1 37 p36 14 p15/sck1 38 p35 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1 41 p34 18 pwm0 42 p33 19 v dd 2 43 p32 20 v ss 2 44 p31 21 p00/an0 45 p30 22 p01/an1 46 p70/int0/t0lcp/an8 23 p02/an2 47 p71/int1/t0hcp/an9 24 p03/an3 48 p72/int2/t0in lc87f5564 a sqfp48 qip48e p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p27/int5 p26/int5 p25/int5 p24/int5 p23/int4 p22/int4 p21/int4 p20/int4 p07/an7 p06/an6 p05/an5 p04/an4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 p36 p35 v dd 3 v ss 3 p34 p33 p32 p31 p30 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 top view
LC87F5564A no.7941-6/19 system block diagram interrupt control standby control ir pla flash rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 pwm0 port 3 port 7 adc int0 to 3 noise rejection filter port 2 int4, 5 acc b register c register psw rar ram stack pointer watch dog timer alu pwm1 base timer timer 6 timer 7 mrc
LC87F5564A no.7941-7/19 pin description pin name i/o function option v ss 1, v ss 2, v ss 3 - power terminal (-) no v dd 1, v dd 2, v dd 3 - power terminal (+) no port 0 p00 to p07 i/o ? 8-bit input/output port ? data direction programmable in nibble units ? pull-up resistor provided/not provided (specified in nibble units) ? hold release input ? port 0 interrupt input ? ad converter input port : an0 (p00) to an7 (p07) yes port 1 p10 to p17 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p10 : sio0 data output p11 : sio0 data input, bus input/output p12 : sio0 clock input/output p13 : sio1 data output p14 : sio1 data input, bus input/output p15 : sio1 clock input/output p16 : timer 1 pwml output p17 : timer 1 pwmh output/buzzer output yes port 2 ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p20 to p23 : int4 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input p24 to p27 : int5 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable p20 to p27 i/o yes port 3 p30 to p36 i/o ? 7-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) yes port 7 ? 4-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p70 : int0 input/hold release input/timer 0l capture input/output for watchdog timer p71 : int1 input/hold release input/timer 0h capture input p72 : int2 input/hold release input/timer 0 event input/timer 0l capture input p73 : int3 input with noise filter/timer 0 event input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o ? ad converter input port : an8 (p70), an9 (p71) no pwm0 o pwm0 output port no pwm1 o pwm1 output port no res i reset terminal no continued on next page.
LC87F5564A no.7941-8/19 continued from preceding page. pin name i/o function option xt1 i ? input terminal for 32.768khz x'tal oscillation ? other function an10 : ad converter input port general input port when not in use, connect terminal to v dd 1. no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? other function an11 : ad converter input port general input port when not in use, set as oscillation and leave terminal open no cf1 i input terminal for ceramic resonator no cf2 o output terminal for ceramic resonator no port output configuration output configuration and pull-up resistor options are shown in the following table. input is possible even when a port is in output mode. terminal option applies to : option output format pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 p20 to p27 p30 to p36 each bit 2 nch-open drain programmable p70 - none nch-open drain programmable p71 to p73 - none cmos programmable pwm0, pwm1 - none cmos none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation none note 1 : programmable pull-up resistor of port 0 is specified in nibble units (p00 to p03, p04 to p07). note : to reduce v dd signal noise and to increase the duration of the backup battery supply, v ss 1, v ss 2 and v ss 3 should connect to each other and they should also be grounded. example 1 : during backup in hold mode, port output "h" level is supplied from the back-up capacitor. continued on next page. power supply back-up capacitor v ss 1 v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
LC87F5564A no.7941-9/19 continued from preceding page. example 2 : during backup in hold mode, output is not held high and its value in unsettled. absolute maximum ratings / ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1 = v dd 2 = v dd 3 -0.3 +6.5 input voltage v i (1) xt1, xt2, cf1 -0.3 v dd +0.3 output voltage v o (1) pwm0, pwm1 -0.3 v dd +0.3 input/output voltage v io (1) ? ports 0, 1, 2 ? ports 3, 7 ? pwm0, pwm1 -0.3 v dd +0.3 v ioph(1) ? ports 0, 1, 2, 3 ? pwm0, pwm1 ? cmos output ? for each pin. -10 peak output current ioph(2) p71 to p73 for each pin. -5 ioah(1) p71 to p73 total of all pins -5 ioah(2) ? port 1 ? pwm0, pwm1 total of all pins -30 ioah(3) port 0 total of all pins -20 high level output current total output current ioah(4) ports 2, 3 total of all pins -20 iopl(1) ? p02 to p07 ? ports 1, 2, 3 ? pwm0, pwm1 for each pin. 20 iopl(2) p00, p01 for each pin. 30 peak output current iopl(3) port 7 for each pin. 5 ioal(1) port 7 total of all pins 15 ioal(2) ? port 1 ? pwm0, pwm1 total of all pins 50 ioal(3) port 0 total of all pins 50 low level output current total output current ioal(4) ports 2, 3 total of all pins 40 ma sqfp48 199 maximum power consumption pd max qip48e ta = -20 to +70c 338 mw operating temperature range topr -20 70 storage temperature range tstg -55 125 c power supply back-up capacitor v ss 1 v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
LC87F5564A no.7941-10/19 recommended operating range / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit 0.294 s tcyc 200 s 4.5 5.5 operating supply voltage range v dd (1) v dd 1 = v dd 2 = v dd 3 0.588 s tcyc 200 s except for on-board rewriting 2.5 5.5 hold voltage vhd v dd 1 = v dd 2 = v dd 3 ram and register data are kept in hold mode. 2.0 5.5 v ih (1) ? ports 1, 2, 3 ? p71 to p73 ? p70 port input/interrupt 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) ? port 0 2.5 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer 2.5 to 5.5 0.9v dd v dd input high voltage v ih (4) xt1, xt2, cf1, res 2.5 to 5.5 0.75v dd v dd v il (1) ? ports 1, 2, 3 ? p71 to p73 ? p70 port input/interrupt 2.5 to 5.5 v ss 0.1v dd +0.4 v il (2) ? port 0 2.5 to 5.5 v ss 0.15v dd +0.4 v il (3) port 70 watchdog timer 2.5 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (4) xt1, xt2, cf1, res 2.5 to 5.5 v ss 0.25v dd v 4.5 to 5.5 0.294 200 operation cycle time tcyc except for on-board rewriting 2.5 to 5.5 0.588 200 s ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty = 505% 4.5 to 5.5 0.1 10 ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty = 505% 2.5 to 5.5 0.1 5 ? leave cf2 pin open ? system clock divider set to 1/2 4.5 to 5.5 0.2 20.4 external system clock frequency fexcf(1) cf1 ? leave cf2 pin open ? system clock divider set to 1/2 2.5 to 5.5 0.1 10 fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 10 fmcf(2) cf1, cf2 5mhz ceramic resonator oscillation refer to figure 1 2.5 to 5.5 5 fmrc rc oscillation 2.5 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 to 5.5 50 mhz oscillation frequency range fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 to 5.5 32.768 khz note 1 : the oscillation parameters are shown on tables 1 and 2. note 2 : v dd 4.5v is required for on-board flash rom rewriting.
LC87F5564A no.7941-11/19 electrical characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 2 ? ports 3, 7 ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in = v dd (including the off-leak current of the output tr.) 2.5 to 5.5 1 i ih (2) xt1, xt2 ? using as an input port ? v in = v dd 2.5 to 5.5 1 input high current i ih (3) cf1 v in = v dd 2.5 to 5.5 15 i il (1) ? ports 0, 1, 2 ? ports 3, 7 ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in = v ss (including the off-leak current of the output tr.) 2.5 to 5.5 -1 i il (2) xt1, xt2 ? using as an input port ? v in = v ss 2.5 to 5.5 -1 input low current i il (3) cf1 v in = v ss 2.5 to 5.5 -15 a v oh (1) i oh = -1.0ma 4.5 to 5.5 v dd -1 v oh (2) ? ports 0, 1, 2, 3 ? pwm0, pwm1 i oh = -0.1ma 2.5 to 5.5 v dd -0.5 output high voltage v oh (3) ports 71, 72, 73 i oh = -0.4ma 4.5 to 5.5 v dd -1 v ol (1) i ol = 10ma 4.5 to 5.5 1.5 v ol (2) i ol = 1.6ma 4.5 to 5.5 0.4 v ol (3) ? ports 0, 1, 2, 3 ? pwm0, pwm1 i ol = 1ma 2.5 to 5.5 0.4 v ol (4) p00, p01 i ol = 30ma 4.5 to 5.5 1.5 v ol (5) output low voltage v ol (6) port 7 i ol = 1ma 2.5 to 5.5 0.4 v pull-up resistor rpu ? ports 0, 1, 2, 3 ? port 7 v oh = 0.9v dd 2.5 to 5.5 15 40 70 k ? hysteresis voltage vhis ? res ? port 1 ? port 2 ? port 7 2.5 to 5.5 0.1v dd v pin capacitance cp all pins ? all pins except the measured terminal : v in = v ss ? f = 1mhz ? ta = 25c 2.5 to 5.5 10 pf
LC87F5564A no.7941-12/19 serial input/output characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle tsck(1) 2 tsckl(1) 1 low level pulse width tsckla(1) 1 tsckh(1) 1 high level pulse width tsckha(1) sck0 (p12), si2p2 refer to figure 6 2.5 to 5.5 3 (sio0) cycle tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1 (p15) refer to figure 6 2.5 to 5.5 1 cycle tsck(3) 4/3 tcyc tsckl(3) ? cmos output ? refer to figure 6 1/2 sck0 (p12) sio0 3/4 low level pulse width tsckla(2) si2p2, si2p3 sio2 1 tsckh(3) 1/2 high level pulse width tsckha(2) sck0 (p12), si2p2 si2p3 sck0 (p12) sio0 2.5 to 5.5 2 tsck cycle tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1 (p15) ? cmos output ? refer to figure 6 2.5 to 5.5 1/2 tsck data set-up time tsdi 0.03 serial input data hold time thdi sb0 (p11), sb1 (p14), si2p1 si0, si1 ? data set-up to si0clk ? data hold from si0clk ? refer to figure 6 2.5 to 5.5 0.03 serial output output delay time tdd0 so0 (p10), so1 (p13), sb0 (o11), sb1 (p14), si2p0 si2p1 ? data hold from si0clk ? time delay from si0clk trailing edge to the so data change in the open drain ? refer to figure 6 2.5 to 5.5 1/3tcyc +0.05 s
LC87F5564A no.7941-13/19 pulse input conditions / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) int0 (p70), int1 (p71), int2 (p72) int4 (p20 to p23) int5 (p24 to p27) ? interrupt acceptable ? timer 0 and 1 event input acceptable 2.5 to 5.5 1 tpih(2) tpil(2) int3 (p73) (the noise rejection clock is selected to 1/1.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 2 tpih(3) tpil(3) int3 (p73) (the noise rejection clock is selected to 1/32.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 64 tpih(4) tpil(4) int3 (p73) (the noise rejection clock is selected to 1/128.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res reset acceptable 2.5 to 5.5 200 s ad converter characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 2) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.10 (tcyc = 0.588 s) 97.92 (tcyc = 3.06 s) ad conversion time = 32 tcyc (adcr2 = 0) (note 3) 3.0 to 5.5 31.36 (tcyc = 0.980 s) 97.92 (tcyc = 3.06 s) 4.5 to 5.5 18.82 (tcyc = 0.294 s) 97.92 (tcyc = 1.53 s) conversion time tcad ad conversion time = 64 tcyc (adcr2 = 1) (note 3) 3.0 to 5.5 62.72 (tcyc = 0.980 s) 97.92 (tcyc = 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain = v dd 3.0 to 5.5 1 analog port input current iainl an0 (p00) to an7 (p07) an8 (p70) an9 (p71) an10 (xt1) an11 (xt2) vain = v ss 3.0 to 5.5 -1 a note 2 : absolute precision excludes the quantizing error (1/2 lsb). note 3 : the conversion time is the time from executing the ad conversion instruction to setting the complete digital conversion value in the register.
LC87F5564A no.7941-14/19 current dissipation characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) ? fmcf = 10mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 to 5.5 18 35 iddop(2) ? cf1 = 20mhz by external clock ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 4.5 to 5.5 19 36 iddop(3) 4.5 to 5.5 10 22 iddop(4) ? fmcf = 5mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1divided 2.5 to 4.5 5 15 iddop(5) 4.5 to 5.5 2 8 iddop(6) ? fmcf = 0hz (when oscillation stops) ? fmx?tal = 32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 1 5 iddop(7) 4.5 to 5.5 2.5 13 iddop(8) ? fmcf = 0hz (when oscillation stops) ? fmx?al = 32.768khz by crystal oscillation ? system clock : 1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 to 4.5 1.8 9 ma iddop(9) 4.5 to 5.5 50 150 current drain during basic operation (note 4) iddop(10) ? fmcf = 0hz (when oscillation stops) ? fmx?al = 32.768khz by crystal oscillation ? system clock : x?tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 30 120 a iddhalt(1) ? halt mode ? fmcf = 10mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 to 5.5 4 10 iddhalt(2) ? halt mode ? cf1 = 20mhz by external clock ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 4.5 to 5.5 4.5 11 iddhalt(3) 4.5 to 5.5 2 5 current drain in halt mode (note 4) iddhalt(4) v dd 1 = v dd 2 = v dd 3 ? halt mode ? fmcf = 5mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1divided 2.5 to 4.5 1 3.0 ma continued on next page.
LC87F5564A no.7941-15/19 continued from preceding page. limits parameter symbol pins conditions v dd [v] min typ max unit iddhalt(5) 4.5 to 5.5 0.5 1.5 iddhalt(6) ? halt mode ? fmcf = 0hz (when oscillation stops) ? fmx?tal = 32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 0.3 1 iddhalt(7) 4.5 to 5.5 1.5 3.6 iddhalt(8) ? halt mode ? fmcf = 0hz (when oscillation stops) ? fmx?tal = 32.768khz by crystal oscillation ? system clock : 1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 to 4.5 1.3 3.3 ma iddhalt(9) 4.5 to 5.5 20 80 current drain in halt mode (note 4) iddhalt(10) v dd 1 = v dd 2 = v dd 3 ? halt mode ? fmcf = 0hz (when oscillation stops) ? fmx?tal = 32.768khz by crystal oscillation ? system clock : x?tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 to 4.5 10 50 iddhold(1) 4.5 to 5.5 0.05 20 current drain during hold mode iddhold(2) v dd 1 ? hold mode ? cf1 = v dd or leave it open (when using external clock) 2.5 to 4.5 0.01 15 iddhold(3) 4.5 to 5.5 15 70 current drain during time- base clock hold mode iddhold(4) v dd 1 ? time-base clock hold mode ? cf1 = v dd or leave it open (when using external clock) ? fmx?tal = 32.768khz by crystal oscillation 2.5 to 4.5 5 40 a note 4 : the current of the output transist ors and pull-up mos transistors are excluded. f-rom write characteristics / ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit on-board writing current iddfw(1) v dd 1 ? 128-byte writing ? including erase time current 4.5 to 5.5 30 65 ma writing time tfw(1) ? 128-byte writing ? including data erase time ? excluding time to fetch 128-byte data 4.5 to 5.5 5.0 10.0 ms main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 1. recommended circuit parameters for the main system clock using the ceramic resonator recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max note csls10m0g53-b0 (15pf) (15pf) 0 ? 4.5 to 5.5v 0.03ms 0.30ms internal c1, c2 10mhz murata cstce10m0g52-r0 (10pf) (10pf) 0 ? 4.5 to 5.5v 0.03ms 0.30ms internal c1, c2 cstls5m00g53-b0 (15pf) (15pf) 0 ? 2.5 to 5.5v 0.03ms 0.30ms internal c1, c2 5mhz murata cstcr5m00g53-r0 (15pf) (15pf) 0 ? 2.5 to 5.5v 0.03ms 0.30ms internal c1, c2 *the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 4)
LC87F5564A no.7941-16/19 subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 2. recommended circuit parameters for th e subsystem clock using the crystal oscillation recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max note 32.768khz seiko epson mc-306 9pf 9pf open 820k ? 2.5 to 5.5v 1.5s 3.0s *the oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a hold mode. (refer to figure 4) notes : since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1 0.5v dd
LC87F5564A no.7941-17/19 reset time and oscillation stabilizing time hold release signal and oscillation stabilizing time figure 4 oscillation stabilizing time v dd limit power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution v dd gnd internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal no hold release signal hold release signal valid tmscf tmsxtal hold halt
LC87F5564A no.7941-18/19 figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res v dd r res res (note) select c res and r res value to assure that at least 200 s reset time is generated after the v dd becomes higher than the minimum operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 si0clk : datain : dataout : dataout : datain : si0clk : dataout : datain : si0clk : tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0) data ram transmission period (only sio0)
LC87F5564A no.7941-19/19 ps

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